Integrated circuit and method for biasing an epitaxial layer

ABSTRACT

An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to an integrated circuit andmethod for biasing an impurity region of an integrated circuitstructure. More particularly, the present invention relates to anintegrated circuit and method for biasing an epitaxial (EPI) layer to alevel substantially equal to a supply voltage (V_(CC)) level yetexhibiting a high reverse breakdown voltage to negative transients ofthe V_(CC) supply.

Traditionally, the accepted method for biasing EPI tubs in bipolarintegrated circuits is by connecting them directly to V_(CC). However,many integrated circuit applications experience negative transientvoltages on the V_(CC) supply line. For example, in some automotiveapplications, transients of up to ±125 volts may be experienced withsource impedances as low as 10 ohms. Similarly, industrial atmospheres,robotics applications and other integrated circuit environments havingrelatively long supply lead lengths may experience such negative voltagetransients.

With negative transient voltages on the V_(CC) line, direct biasing ofthe EPI tubs may result in a forward biased diode from the P typesubstrate, which is nominally tied to a circuit ground potential, to theEPI region. Large negative voltage transients on the V_(CC) line maytherefore result in the destruction of the EPI substrate junction orinterconnecting metallization.

One previously utilized method for dealing with negative voltagetransients has been to eliminate the possibility of current flow in thisforward biased diode from the EPI substrate junction by application ofV_(CC) to a P region to provide a high reverse breakdown voltage diodefrom V_(CC) to the EPI region. In many applications, however, it isnecessary that the EPI regions be held at a voltage less than one diodevoltage from V_(CC) for example, in power BIMOS circuits where thesubstrate is essentially V_(OUT) and may go as high as the level ofV_(CC). Such circuits may be susceptible to latching should thesubstrate go to V_(CC) and inject holes into an EPI region biased belowV_(CC) when a signal path P region within the EPI collects. Latchingwill occur if this P region collecting has positive phase to the output,that is, collected current turns on the output forcing the substrate toa higher level.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide animproved integrated circuit and method for biasing an epitaxial layer.

It is further an object of the present invention to provide an improvedintegrated circuit and method for biasing an epitaxial layer which isreadily fabricated utilizing a minimum of on-chip area.

It is still further an object of the present invention to provide animproved integrated circuit and method for biasing an epitaxial layer toa level substantially equal to V_(CC) yet having a very high reversebreakdown voltage to negative voltage transients on V_(CC).

The foregoing and other objects are achieved in the present inventionwherein there is provided an integrated circuit and method including acircuit for biasing a first portion of an impurity region of theintegrated circuit to a voltage level substantially equal to a supplyvoltage level while having a high reverse breakdown voltage to negativetransients of the supply voltage level. A contact transistor is formedwithin a second, isolated portion of the impurity region of theintegrated circuit and has first, second and third contact leadsthereto, the first contact lead being coupled to a supply voltage line,the second contact lead being coupled to a bias voltage line and thethird contact lead being connected to the first portion of the impurityregion. An integrated circuit and method in accordance with the presentinvention may further comprise a shunt diode having anode and cathodeterminals thereof, the anode and cathode terminals being respectivelyconnected to the first and third contact leads of the contacttransistor. In certain embodiments, in accordance with the presentinvention, the shunt diode comprises a shunt transistor havingrespective first, second and third shunt leads thereto, the first shuntlead forming the anode terminal and the second and third shunt leadsbeing common connected to form the cathode terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above mentioned and other features and objects of the invention andthe manner of attaining them will become more apparent and the inventionitself will be best understood by reference to the following descriptionof an embodiment of the invention taken in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a simplified cross-sectional view of an integrated circuitillustrating two prior art techniques for biasing an epitaxial layer;

FIG. 2 is a simplified cross-sectional view of an integrated circuitillustrating the latching problems inherent in a prior art device inaccordance with a portion of FIG. 1 having its substrate at V_(CC), anEPI region at V_(CC) -V_(BE) and a signal path P region acting as acollector;

FIGS. 3A and 3B are a simplified cross-sectional view and partialschematic representation respectively of a biasing circuit in accordancewith the present invention illustrating the biasing of an impurityregion, for example, an epitaxial layer by means of a saturated PNPcurrent source functioning as a contact transistor;

FIGS. 4A and 4B are partial schematic and cross-sectional views of aportion of an integrated circuit in accordance with the presentinvention illustrating the addition of a high voltage diode, inparticular, a PNP diode in parallel with the saturated PNP currentsource of FIGS. 3A and 3B;

FIG. 5 is a schematic illustration of a portion of a prior art BIMOScircuit illustrating the diodes formed between a P type resistor andDMOS device wells coupled to ground formed in an epitaxial layer coupledto a supply voltage, V_(CC), which might under certain circumstances,experience a negative voltage transient;

FIG. 6 is a schematic representation of the BIMOS circuit of FIG. 5showing the coupling of the epitaxial layer containing a resistor andDMOS device to V_(CC) through a high voltage diode when the substrate isat V_(CC), as shown by a switched PNP transistor; and

FIG. 7 is a further schematic representation of the BIMOS circuit ofFIG. 6 showing the coupling of the epitaxial layer containing a resistorand DMOS device to V_(CC) through a saturated PNP current sourcefunctioning as a contact transistor and high voltage diode when thesubstrate is at V_(CC), as shown by a switched PNP transistor.

DESCRIPTION OF A PREFERRED EMBODIMENT

With reference to FIG. 1, a portion of a prior art integrated circuit 10is shown. Integrated circuit 10 comprises, in major part, P substrate 12and N epitaxial layers 14, 16 separated by a plurality of isolationregions 18. A P region 20 is disposed within N epitaxial layer 16. Asource of supply voltage V_(CC) is applied directly to N epitaxial layer14 and P region 20. P substrate 12 is connected to circuit ground.

The usual method of biasing EPI tubs in bipolar integrated circuits isby connecting the epitaxial layer directly to V_(CC). This is shown bythe connection of N epitaxial layer 14 to a supply voltage V_(CC).However, should a negative transient appear on V_(CC) with N epitaxiallayer 14 connected directly thereto while P substrate 12 is connected tocircuit ground, a forward biased diode will result at the interface of Nepitaxial layer 14 with P substrate 12. Large negative voltagetransients will then result in destruction of the junction between Nepitaxial layer 14 and P substrate 12 or, could possibly adverselyimpact any interconnecting metallization used in integrated circuit 10.

With a view towards eliminating the possibility of this forward biaseddiode, P region 20 could serve as a high reverse breakdown diode to thesupply voltage V_(CC). Thus, N epitaxial layer 16 will be tied to thesupply voltage V_(CC) through P region 20 resulting in a PN diode whichis reverse biased to negative transients of V_(CC).

Referring additionally now to FIG. 2, the use of P region 20 inapplications where it is necessary that N epitaxial layer 16 be heldvery near the level of V_(CC) is shown. In the portion of integratedcircuit 10 herein shown, P substrate 12 is at the level of V_(CC) suchas would be the case in power BIMOS and other devices in which thesubstrate is at or near V_(CC) and functions as V_(OUT). In theembodiment of FIG. 2, similar structure to that above described withrespect to FIG. 1 is similarly numbered and the foregoing descriptionthereof will suffice herefor.

With respect to that portion of integrated circuit 10 shown in FIG. 2,such structure may be susceptible to latching if P substrate 12 is at ornear the supply voltage level V_(CC) and holes are injected into Nepitaxial layer 16 which is then one V_(BE) below V_(CC) and a signalpath is established wherein P region 20 functions as a collector of aPNP transistor. Latching will occur if P region 20 collecting exhibitspositive phase with respect to the output V_(OUT). That is, collectedcurrent turns on the output forcing P substrate 12 to a higher level. Inthis manner, P region 20 can supply a collected current output 22 fromsubstrate 12 in the signal path as positive feedback.

Referring additionally now to FIGS. 3A and 3B, a portion of anintegrated circuit 30 is shown in accordance with the present inventionin which a reverse biased high voltage diode is maintained yet anepitaxial region may be at a voltage level close to V_(CC). Integratedcircuit 30 comprises, in pertinent part, a P substrate 12 and Nepitaxial layers 32, 34 separated by a plurality of isolation regions18. A PNP transistor 28, functioning as a contact transistor, is formedwithin N epitaxial layer 34, and in the embodiment shown, comprises amulti-collector saturated device having collectors 38, an emitter 36connected to V_(CC) and a base 40 connected to a source of bias voltage.Collectors 38 are utilized to bias N epitaxial layers 32. Although PNPtransistor 28 resides in N epitaxial layer 34 which is maintained at alevel of one V_(BE) below V_(CC) no problem is presented as abovedescribed because a high substrate injection results in collectors 38collecting even more current to bias the associated N epitaxial layers32.

Referring additionally now to FIGS. 4A and 4B, an alternative embodimentto provide biasing to N epitaxial layers 32 is shown. In thisembodiment, PNP transistor 28 which is functioning as a saturated PNPcurrent source has an additional diode 42 connected in paralleltherewith. Diode 42 is shown schematically as having its anode connectedto emitter 36 and its cathode connected to one of collectors 38. Inpractice, diode 42 may be a PNP transistor having its emitter commonconnected with emitter 36 and its base and collector common connectedwith one of collectors 38. Diode 42 may be useful due to the fact thatunder transient conditions, the current through N epitaxial layer 32 maybecome larger than the normal leakage current and the collector 38 ofPNP transistor 28 may be unable to supply the necessary current whereina latch condition may develop. In order to avoid this possiblesituation, both PNP transistor 28 and diode 42 may be utilized to bias Nepitaxial layer 32.

Additionally, in the circuit "off" state, i.e. when P substrate 12 islow, it may be desirable to turn off the bias line, which, without diode42 would leave N epitaxial layer 32 floating. Under such conditions,when the circuit is enabled, P substrate 12 might rise faster than thebias line and create a latch condition. Diode 42 functions to hold Nepitaxial layer 32 high thereby avoiding a floating condition.

Referring additionally now to FIG. 5, a portion of a prior art BIMOScircuit 60 is shown. For illustrative purposes, BIMOS circuit 60 isshown as comprising a series connected resistor 44 and current source 52coupled between ground and V_(CC). Similarly, a MOSFET 46 is connectedin series with current source 54 between ground and V_(CC). The gate ofMOSFET 46 is connected between current source 52 and resistor 44.Current sources 52 and 54, shown as PNP transistors, have their emitterterminals connected to V_(CC) and their collector terminals respectivelyconnected to resistor 44 and MOSFET 46. The base terminals of currentsources 52, 54 are connected to a source of bias voltage. Alsoillustrated are parasitic diodes 48, 50 from the P type resistor 44 andMOSFET 46 well respectively to an N type epitaxial layer. This N typeepitaxial layer is shown as connected to V_(CC).

In operation, if the supply voltage V_(CC) experienced a negativetransient, then it is possible that parasitic diodes 48, 50 would becomeforward biased into the epitaxial layer such that large currents couldflow. Thus, it is possible that the P well of MOSFET transistor 46 aswell as the P region of resistor 44 which are both tied to ground, couldforward bias parasitic diodes 48 and 50 from ground to V_(CC) whenV_(CC) went negative.

Referring additionally now to FIG. 6, a further extension of BIMOScircuit 60 of FIG. 5 is shown. In this application, a diode 42, which isshown as a PNP transistor having its base connected to its collector,couples the cathodes of parasitic diodes 48 and 50 to V_(CC). In thismanner, a reverse biased diode serves to protect the epitaxial layer inwhich resistor 44 and MOSFET 46 are formed from negative voltagetransients of V_(CC). However, as previously described with respect toFIG. 2 in particular, problems could develop when the substrate of BIMOScircuit 60 is at V_(CC) as shown by means of a switched PNP transistor.The emitter of this transistor is the substrate, the base is any EPIregion a V_(BE) below the emitter and the collector is any P regionwithin the EPI. Should the substrate go as high as V_(CC), when anepitaxial layer is at a level of V_(CC) -V_(BE), the substrate will thenforward bias from the substrate to the epitaxial layer and any Pregions, such as resistor 44 or the P well of MOSFET 46 could becomecollectors for the substrate to EPI current. This problem is inherentdue to the use of diode 42 placing the EPI at a V_(BE) below V_(CC) whenit is possible that the substrate itself might be at a level equal toV_(CC) as shown.

Referring additionally now to FIG. 7, BIMOS circuit 60 is shown havingits epitaxial layer biased in accordance with the present invention. Inthis extension of FIGS. 5 and 6, diode 42 is paralleled with a saturatedPNP current source acting as a contact transistor comprising PNPtransistor 28. Under normal operation, when PNP transistor 28 turns on,the voltage applied to the epitaxial layer is pulled within a saturationvoltage of V_(CC). Diode 42 then, in effect, is not a factor.Resultantly, the substrate PNP device comprising the substrate,epitaxial layer and any P region can't turn on because when thesubstrate is at V_(CC) the epitaxial layer is not down 1 V_(BE). Inpractice, the epitaxial layer is below V_(CC) by approximately 100 to200 millivolts. Moreover, should V_(CC) go negative, PNP transistor 28reverse biases and turns off. Since it is a high voltage transistor, itpresents a high breakdown voltage in the reverse direction should V_(CC)go negative. Diode 42 would function in case of a transient phenomenonwhich might occur if there is more current demanded by the epitaxiallayer than the current source can handle. Therefore, diode 42 inparallel with PNP transistor 28 insures that the voltage can never golower than 1 V_(BE). Should the epitaxial layer approach a level lowerthan 1 V_(BE) below V_(CC), diode 42 will forward bias and supply thenecessary amount of current. Moreover, when no bias is applied to PNPtransistor 28, diode 42 will function to hold the epitaxial layers upwithin one V_(BE) of V_(CC).

What has been provided therefore is an improved integrated circuit andmethod for biasing an epitaxial layer which is readily fabricatedutilizing a minimum of on-chip area. The integrated circuit and methodof the present invention provides a means for biasing an epitaxial layerclose to a supply voltage level V_(CC) yet exhibiting a high reversebreakdown voltage to negative voltage transients on V_(CC).

While there have been described above the principles of the invention inconjunction with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationto the scope of the invention.

We claim:
 1. A circuit for biasing a first portion of an impurity regionof an integrated circuit to a voltage level substantially equal to asupply voltage level comprising:a contact transistor formed within asecond isolated portion of said impurity region and having first, secondand third contact leads thereto, said first contact lead being coupledto a supply voltage line, said second contact lead being coupled to abias voltage line and said third contact lead being connected to saidfirst portion of said impurity region; and a shunt diode having anodeand cathod terminals thereof, said anode and cathod terminals beingrespectively connected to said first and third contact leads of saidcontact transistor.
 2. The biasing circuit of claim 1 wherein said diodecomprises a shunt transistor having respective first, second and thirdshunt leads thereto, said first shunt lead forming said anode terminaland said second and third shunt leads being common connected to formsaid cathode terminal.
 3. The biasing circuit of claim 1 wherein saidimpurity region is an epitaxial layer.
 4. The biasing circuit of claim 1wherein said contact transistor is a PNP bipolar device.
 5. The biasingcircuit of claim 2 wherein said shunt transistor is a PNP bipolardevice.
 6. A method for biasing a first portion of an impurity region ofan integrated circuit to a voltage level substantially equal to a supplyvoltage level while having a high reverse breakdown voltage to negativetransients of said supply voltage level comprising the steps of:forminga contact transistor within a second isolated portion of said impurityregion having first, second and third contact leads thereto; firstlycoupling said first contact lead to a supply voltage line; secondlycoupling said contact lead to a bias voltage line; connecting said thirdcontact lead to said first portion of said impurity region; andproviding a shunt diode having anode and cathode terminals thereof, saidanode and cathode terminals being connected to said first and thirdcontact leads of said contact transistor.
 7. The method of claim 6wherein said step of providing is carried out by means of a shunttransistor having respective first, second and third shunt leadsthereto, said first shunt lead forming said anode terminal and saidsecond and third shunt leads being common connected to form said cathodeterminal.
 8. An integrated circuit including a circuit for biasing afirst portion of an impurity region of said integrated circuit to avoltage level substantially equal to a supply voltage level while havinga high reverse breakdown voltage to negative transients of said supplyvoltage level comprising:a contact transistor formed within a secondisolated portion of said impurity region of said integrated circuit andhaving first, second and third contact leads thereto, said first contactlead being coupled to a supply voltage line, said second contact leadbeing coupled to a bias voltage line and said third contact lead beingconnected to said first portion of said impurity region; and a shuntdiode having anode and cathode terminals thereof, said anode and cathodeterminals being respectively connected to said first and third contactleads of said contact transistor.
 9. The integrated circuit of claim 8wherein said diode comprises a shunt transistor having respective first,second and third shunt leads thereto, said first shunt lead forming saidanode terminal and said second and third shunt leads being commonconnected to form said cathode terminal.
 10. The integrated circuit ofclaim 8 wherein said impurity region is an epitaxial layer.
 11. Theintegrated circuit of claim 8 wherein said contact transistor is a PNPbipolar device.
 12. The integrated circuit of claim 9 wherein said shunttransistor is a PNP bipolar device.